`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   16:58:12 09/27/2011
// Design Name:   REG_ALU_LOGIC
// Module Name:   C:/Users/Chase/16bitcpu/LCD_fibonauchi.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: REG_ALU_LOGIC
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module LCD_fibonauchi;

	// Inputs
	reg CLK;
	reg reset;
	reg [3:0] reg1;
	reg [3:0] reg2;
	reg wr_en;
	reg [3:0] write_address;
	reg A_Enable;
	reg B_Enable;
	reg op;
	reg Cin;
	reg [4:0] F;
	reg reg2_data;

	// Instantiate the Unit Under Test (UUT)
	REG_ALU_LOGIC uut (
		.CLK(CLK), 
		.reset(reset), 
		.reg1(reg1), 
		.reg2(reg2), 
		.wr_en(wr_en), 
		.write_address(write_address), 
		.A_Enable(A_Enable), 
		.B_Enable(B_Enable), 
		.op(op), 
		.Cin(Cin), 
		.F(F), 
		.reg2_data(reg2_data)
	);
	S3Etest(CLK, reset, SF_CE0, SF_D, LCD_E, LCD_RS, LCD_RW);
	initial begin
		// Initialize Inputs
		CLK = 0;
		reset = 0;
		reg1 = 0;
		reg2 = 0;
		wr_en = 0;
		write_address = 0;
		A_Enable = 0;
		B_Enable = 0;
		op = 0;
		Cin = 0;
		F = 0;
		reg2_data = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule

